This invention relates generally to computer systems, and more particularly to detection of a faulty lanes in a transmission medium.
One approach to locating a failing lane (i.e. a lane with data errors) in a transmission medium, such as a bus, is to use an error correcting code (ECC). An ECC can detect and correct a number of failing bits, but requires more redundant bits than an error detection code (e.g., a cyclical redundancy code or “CRC”). In addition, an ECC can be used to detect specific bits that are failing (the number of bits detectable depending on the particular ECC code being implemented); however a drawback of ECC is that it does not determine when it is time declare a failing lane as faulty and to replace it. Typically, an error detection code can detect an error but is not capable of fully resolving the physical nature of the error; for example, it may not be able to fully identify a failing lane for all possible error patterns in the failing lane. Therefore, a drawback of using an error detection code is that may not accurately isolate errors to specific failing lanes. Another approach to detecting a failing lane is lane shadowing, where a copy of data is sent on spare lanes. However, a drawback to lane shadowing is that it only operates on a subset of lanes at any point in time and can miss error events occurring outside of the analysis window for a given failing lane.
Accordingly, and while existing techniques for dealing with error detection and correction may be suitable for their intended purpose, there remains a need in the art for e schemes that overcome these drawbacks in relation to detecting faulty lanes.